1. Field of the Invention
The present invention relates to a semiconductor device having element isolation regions and, more particularly, to a semiconductor device having an improved junction structure of element isolation regions having different shapes.
2. Description of the Related Art
In general, when a plurality of circuit elements are to be formed on the major surface of a semiconductor device, the circuit elements must be electrically isolated from each other. As representative element isolation techniques used in this case, there are local oxidation of the silicon (LOCOS) and trench isolation. An insulation structure is formed by a method obtained by combining these techniques.
An element isolation layer made of an insulator and formed by the LOCOS method to electrically isolate an element region is a relatively wide element isolation layer and can isolate an element region having a wide area. In particular, according to the LOCOS method, an element isolation layer having highly reliable electric isolation can be easily formed.
The trench isolation method is performed as follows. A trench is formed in the surface of a semiconductor substrate using anisotropic etching or the like, and the trench is filled with an insulator to form a trench insulating layer, thereby isolating an element region.
According to the trench isolation method, a fine element isolation region which cannot be obtained by the LOCOS method can be formed.
That is, when the LOCOS method and the trench isolation method are used at the same time, a fine element isolation region and a wide element isolation region can be easily combined to be formed.
However, a junction portion of element isolation regions having different shapes and consisting of a fine element isolation region and a wide element isolation region in a semiconductor integrated circuit is present between these element isolation regions. It is almost impossible to prevent formation of the junction portion by a pattern layout. On the contrary, when the junction portion is provided, the pattern layout can be easily designed.
When a pattern layout obtained by perpendicularly bonding the trench element isolation region to the LOCOS element isolation region is employed in a junction portion of these element isolation regions, electric isolation must be assured. Therefore, both the element isolation regions are formed to overlap each other.
A structure at the overlapping portion is more complex than an isolation structure formed by a single element isolation region consisting of, e.g., a LOCOS element isolation region. In addition, since stress generated by thermal expansion or the like in the step of forming an element isolation region is easily concentrated on an overlapping portion between an element region and an element isolation region in a semiconductor substrate, crystal defects may occur in the semiconductor substrate near the junction portion depending on a shape of the junction portion.
When an impurity is to be diffused in self-alignment in an element region using the element isolation region as a mask to form an impurity diffusion layer, a voltage is applied to the substrate during diffusion to generate an electric field at a corner of the diffusion layer. The electric field is concentrated on a specific portion due to the shape of an overlapping portion of the element isolation regions. Therefore, breakdown voltage characteristics are conspicuously degraded, and a junction breakdown voltage is decreased.
That is, according to the above conventional junction structure, occurrence of crystal defects in a semiconductor substrate near the junction portion is encouraged in the step of forming an element isolation region, and a junction breakdown voltage is decreased compared with a junction structure consisting of the same element isolation region.